The present invention relates to a semiconductor device, especially to technology which is effective when applied to a semiconductor device provided with memory units, such as an SRAM.
Patent Literature 1, for example, discloses a semiconductor storage device which generates a sense amplifier enable signal using a dummy circuit provided with plural dummy cells. Patent Literature 2 discloses that, in a semiconductor storage device of a single bit line system in which a read operation timing is decided by operation of a replica bit line, the semiconductor storage device is configured such that a gate length of a replica memory cell transistor coupled to the replica bit line is set to be longer than a gate length of a proper memory cell transistor. Patent Literature 3 discloses a semiconductor integrated circuit device which is provided with a first replica bit line and a second replica bit line respectively coupled to a replica memory cell and with an inverter circuit for inputting an output of the first replica bit line to the second replica bit line, and which generates a sense amplifier enable signal by use of the divided replica bit lines.
(Patent Literature)
(Patent Literature 1) Japanese Patent Laid-open No. 2004-95058
(Patent Literature 2) Japanese Patent Laid-open No. 2006-31752
(Patent Literature 3) Japanese Patent Laid-open No. 2010-165415